1. Technical Field
This disclosure relates to electrical circuits, including signal-processing circuits and systems.
2. Related Art
Signal-processing circuits and systems may be used in a wide range of applications, including, but not limited to, audio, automotive, data acquisition, industrial control, medical diagnostics and treatment, navigation, radar detection, seismology, and sensors.
A signal-processing operation of a configurable signal-processing circuit may be selected to be one of several predefined selectable signal-processing operations.
FIG. 1A shows a prior-art configurable signal-processing circuit/system 100. An input signal may be an input sequence of values I(n) received at a first sample rate. An exemplary first sample rate may be 1 million values (samples) received per second, corresponding to a period of the first sample rate of 1 micro-second (one millionth of a second). An output signal may be an output sequence of values O(k) provided at a second sample rate. An exemplary second sample rate may be 250 thousand values outputted per second, corresponding to a period of the second sample rate of 4 micro-seconds. For some selectable configurations of configurable signal-processing circuit 100, a first sample rate of input I(n) may be equal to a second sample rate of output O(k). For other selectable configurations of the circuit 100, the first and second sample rates may be distinct. A ratio of an input (first) sample rate divided by an output (second) sample rate may be referred to as a sample-rate ratio (SRR). An exemplary sample-rate ratio may be characterized as 1,000,000/250,000, 4:1, or 4.
Individual values comprised in an input sequence I(n) may be indexed (pointed to) by individual values of a first sequence index n. For example, a first value in an exemplary sequence I(n)=3, 6, 22, 8, 6, . . . , is I(1)=3, a second value therein is I(2)=6, a third value therein is I(3)=22, and so forth. Likewise, individual values comprised in an output sequence O(k) may be indexed by individual values of a second sequence index k. First sequence index n increments at the first sample rate of I(n). Second sequence index k increments at the second sample rate of O(k).
FIG. 1B shows an exemplary timing diagram for an input sequence I(n), output sequence O(k), and sample-rate ratio of 4:1. A first (input) timing waveform WI(t) may be provided to indicate instances in time (e.g., at low-to-high transitions) when individual values of input sequence I(n) are steady (ready) and may be evaluated (read) reliably by configurable signal-processing circuit 100 (FIG. 1A). Circuit 100 may provide a second (output) timing waveform WO(t) for indicating instances in time when individual values of output sequence O(k) are steady (ready) and may be evaluated (read) reliably by an external circuit (not shown) receiving O(k).
First and second timing waveforms, WI(t) and WO(t), may be optional and may be not received and/or provided by some configurable signal-processing circuits. For example, an external circuit (not shown) may provide I(n), WI(t), and a configuration code CC to a configurable signal-processing circuit 100 (FIG. 1A), and it may receive only sequence O(k) back from circuit 100. A specification document (data sheet) for circuit 100 may provide values for timing parameters that may enable the external circuit to reliably read each value of the output sequence O(k) without relying upon (or having access to) WO(t).
Configurable signal-processing circuit 100 (FIG. 1A) receives a configuration code CC that selects one of several selectable predefined signal-processing operations. For example, a first segment of the configuration code may select a type of filter for a filtering operation. A second segment of the configuration code may select a sample-rate ratio.
FIG. 2 shows a configuration table for an exemplary configurable signal-processing circuit. A four-bit configuration code CC selects one of 16 selectable combinations of a filter type and a sample-rate ratio. Sample-rate ratios that are greater than one (e.g., 4:1 and 16:1) may be selected to configure the exemplary circuit to operate as a decimation filter. Sample-rate ratios that are smaller than one (e.g., 1:4 and 1:16) may be selected to configure the exemplary circuit to operate as an interpolation filter. Decimation and interpolation filter circuits may be implemented as described by Eugene B. Hogenauer in a paper titled “An Economical Class of Digital Filters for Decimation and Interpolation,” which was published in the April 1981 issue of “IEEE Transactions on Acoustics, Speech, and Signal Processing”. This paper by Hogenauer is incorporated herein by reference for describing theory, operation, and practical implementation of decimation and interpolation filters, including (but not limited to) such circuits based on Cascaded-Integrator-Comb (CIC) filters of any order. CIC filters may be a hardware-efficient implementation of a filter type commonly known as SINC filters. Decimation filters, interpolation filters, and many other types of signal-processing operations and circuits are described in literature including professional journals, text books, and patents.
Persons skilled in the art will recognize that a regular structure of CIC filters facilitates configuring and re-configuring circuitry to provide a plurality of selectable signal-processing operations. For example, circuitry configured to operate as a fourth-order CIC filter may be re-configured to operate as a CIC filter of first-, second-, or third-order. FIG. 6 in the paper by Hogenauer shows that a multiplexer circuit may be provided to configure a fourth-order CIC filter to operate with a selectable sample-rate ratio. Re-configuration and re-use of circuitry for a configurable signal-processing circuit may be advantageous, but it is not necessary. For example, distinct dedicated circuitry may be provided for each selectable predefined signal-processing operation. Multiplexer circuits may be responsive to a configuration code to configure a signal path from an input to an output via dedicated circuitry providing a selected signal-processing operation.
Configurable signal-processing circuit 100 of FIG. 1A may provide a plurality of selectable signal-processing operations of substantially any type. Some selectable signal-processing operations may be of a substantially non-linear nature (not just time-variant). For example, a value of an output sequence O(k) may be a root-mean-square (rms) value of a plurality of values comprised in an input sequence I(n). Another selectable signal-processing operation may provide a transformation-type operation. For example, values of output sequence O(k) may be derived by Fourier Transformations applied to segments of input sequence I(n), and O(k) may be a frequency-domain representation of a signal. Such segments of I(n) may be overlapping, back-to-back, or sparse, corresponding to a sample-rate ratio that may be either greater than, equal to, or smaller than one. Other selectable signal-processing operations may provide a filtering operation with a selectable frequency response for one or more selectable sample-rate ratios. An exemplary signal-processing circuit may be configurable to selectively operate as a decimation filter, as an interpolation filter, or as a conventional filter with a sample-rate ratio of one. Several options for an overall frequency response from I(n) to O(k) may be selectable for some or all selectable sample-rate ratios. Accordingly, a configurable signal-processing circuit 100 (FIG. 1A) may provide a wide range of predefined selectable signal-processing operations.
Providing a configuration code CC to a configurable signal-processing circuit 100 (FIG. 1A) may be a relatively trivial matter if the circuit 100 is comprised within a fully-integrated system on a chip (such as a single-die integrated-circuit chip). For example, providing a configuration code CC of FIG. 2 to circuit 100 of FIG. 1A from another circuit block within a fully-integrated system on a chip may require relatively few wires and/or other types of internal connections, which may represent a negligible cost (i.e., a modest allocation of an abundant resource). The situation may be quite different when circuit 100 is physically separated from a circuit providing a configuration code. For example, if circuit 100 is implemented as an integrated-circuit chip enclosed in a separate package mounted on a printed circuit board, then receiving a configuration code from a circuit that is external to the package may involve a considerable allocation of a substantially limited resource. Specifically, one or more pins of the package may be dedicated to receiving the configuration code. The point here is not that it necessarily is technically challenging to provide or receive a configuration code, but rather that it may be undesirable to allocate a substantially limited resource for that purpose.
It is often desirable to shrink a physical size of a device incorporating signal processing, for example a medical device. Integrated-circuit chips may be enclosed in progressively smaller and smaller packages, which may have fewer and fewer pins available for making connections to an enclosed integrated-circuit chip. It may be undesirable to dedicate 4 pins of an integrated-circuit package for receiving an exemplary 4-bit configuration code, especially if a total number of pins for the package is relatively small, say 8, 10, or 12. It is well-known that a configuration code may be received via a digital serial interface, and that may be done to limit a number of pins dedicated to receiving a multi-bit configuration code to only one. However, it may be undesirable to dedicate even a single pin for this purpose. Furthermore, it may cause an external circuit to be constrained by another substantially limited resource. For example, an external circuit may not have a (spare) port available for digital serial communication of a configuration code.
What is needed is circuits and methods for configuring a configurable signal-processing circuit without dedicating any connections (e.g., pins of a package or other ports) exclusively for selecting a predefined signal-processing operation.
What is needed is a substantially self-configuring signal-processing circuit.